mosfets silicon n-channel mos ( -mos ) TK4P60D 1. 1. 1. 1. applications applications applications applications ? switching voltage regulators 2. 2. 2. 2. features features features features (1) low drain-source on-resistance: r ds(on) = 1.4 ? (typ.) (2) high forward transfer admittance: |y fs | = 2.5 s (typ.) (3) low leakage current: i dss = 10 a (max) (v ds = 600 v) (4) enhancement mode: v th = 2.4 to 4.4 v (v ds = 10 v, i d = 1 ma) 3. 3. 3. 3. packaging and internal circuit packaging and internal circuit packaging and internal circuit packaging and internal circuit 1: gate (g) 2: drain (d)(heatsink) 3: source (s) dpak 4. 4. 4. 4. absolute maximum ratings (note) (t absolute maximum ratings (note) (t absolute maximum ratings (note) (t absolute maximum ratings (note) (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics drain-source voltage gate-source voltage drain current (dc) drain current (pulsed) power dissipation single-pulse avalanche energy avalanche current reverse drain current (dc) reverse drain current (pulsed) channel temperature storage temperature (t c = 25 ) (note 1) (note 1) (note 2) (note 3) (note 1) (note 1) symbol v dss v gss i d i dp p d e as i ar i dr i drp t ch t stg rating 600 30 4 16 100 158 4 4 16 150 -55 to 150 unit v a w mj a note: using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. www.freescale.net.cn www.freescale.net.cn 1/8 7 . 3 ' 0 2 6 ) ( 7 v 6 l o l f r q 1 & k d q q h o 0 2 6 ? ? ? ? ? ? ? ? ? ? ?? ??? ' 3 $ .
5. 5. 5. 5. thermal characteristics thermal characteristics thermal characteristics thermal characteristics characteristics channel-to-case thermal resistance channel-to-ambient thermal resistance symbol r th(ch-c) r th(ch-a) max 1.25 125 unit /w note 1: ensure that the channel temperature does not exceed 150 . note 2: v dd = 90 v, t ch = 25 (initial), l = 17.3 mh, r g = 25 ? , i ar = 4 a note 3: repetitive rating; pulse width limited by maximum channel temperature note: this transistor is sensitive to electrostatic discharge and should be handled with care. www.freescale.net.cn www.freescale.net.cn 2/8 7 . 3 ' 7 k h u p d o & k d u d f w h u l v w l f v 7 k h u p d o & k d u d f w h u l v w l f v 7 k h u p d o & k d u d f w h u l v w l f v 7 k h u p d o & k d u d f w h u l v w l f v & k d u d f w h u l v w l f v & k d q q h o w r f d v h w k h u p d o u h v l v w d q f h & k d q q h o w r d p e l h q w w k h u p d o u h v l v w d q f h 6 \ p e r o 5 w k f k f 5 w k f k d 0 d [ 8 q l w : 1 r w h ( q v x u h w k d w w k h f k d q q h o w h p s h u d w x u h g r h v q r w h [ f h h g 1 r w h 9 ' ' 9 7 f k l q l w l d o / p + 5 * ? ?????
6. 6. 6. 6. electrical characteristics electrical characteristics electrical characteristics electrical characteristics 6.1. 6.1. 6.1. 6.1. static characteristics (t static characteristics (t static characteristics (t static characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics gate leakage current drain cut-off current drain-source breakdown voltage gate threshold voltage drain-source on-resistance forward transfer admittance symbol i gss i dss v (br)dss v th r ds(on) |y fs | test condition v gs = 30 v, v ds = 0 v v ds = 600 v, v gs = 0 v i d = 10 ma, v gs = 0 v v ds = 10 v, i d = 1 ma v gs = 10 v, i d = 2 a v ds = 10 v, i d = 2 a min 600 2.4 0.7 typ. 1.4 2.5 max 1 10 4.4 1.7 unit a v ? s 6.2. 6.2. 6.2. 6.2. dynamic characteristics (t dynamic characteristics (t dynamic characteristics (t dynamic characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics input capacitance reverse transfer capacitance output capacitance switching time (rise time) switching time (turn-on time) switching time (fall time) switching time (turn-off time) symbol c iss c rss c oss t r t on t f t off test condition v ds = 25 v, v gs = 0 v, f = 1 mhz see figure 6.2.1. min typ. 600 4 70 18 40 8 55 max unit pf ns fig. fig. fig. fig. 6.2.1 6.2.1 6.2.1 6.2.1 switching time test circuit switching time test circuit switching time test circuit switching time test circuit 6.3. 6.3. 6.3. 6.3. gate charge characteristics (t gate charge characteristics (t gate charge characteristics (t gate charge characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics total gate charge (gate-source plus gate-drain) gate-source charge gate-drain charge symbol q g q gs q gd test condition v dd 400 v, v gs = 10 v, i d = 4 a min typ. 12 7 5 max unit nc 6.4. 6.4. 6.4. 6.4. source-drain characteristics (t source-drain characteristics (t source-drain characteristics (t source-drain characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics diode forward voltage reverse recovery time reverse recovery charge symbol v dsf t rr q rr test condition i dr = 4 a, v gs = 0 v i dr = 4 a, v gs = 0 v -di dr /dt = 100 a/ s min typ. 1200 7 max -1.7 unit v ns c www.freescale.net.cn www.freescale.net.cn 3/8 7 . 3 ' ( o h f w u l f d o & k d u d f w h u l v w l f v ( o h f w u l f d o & k d u d f w h u l v w l f v ( o h f w u l f d o & k d u d f w h u l v w l f v ( o h f w u l f d o & k d u d f w h u l v w l f v 6 w d w l f & k d u d f w h u l v w l f v 7 6 w d w l f & k d u d f w h u l v w l f v 7 6 w d w l f & k d u d f w h u l v w l f v 7 6 w d w l f & k d u d f w h u l v w l f v 7 d d d d x q o h v v r w k h u z l v h v s h f l i l h g x q o h v v r w k h u z l v h v s h f l i l h g x q o h v v r w k h u z l v h v s h f l i l h g x q o h v v r w k h u z l v h v s h f l i l h g & k d u d f w h u l v w l f v * d w h o h d n d j h f x u u h q w ' u d l q f x w r i i f x u u h q w ' u d l q v r x u f h e u h d n g r z q y r o w d j h * d w h w k u h v k r o g y r o w d j h ' u d l q v r x u f h r q u h v l v w d q f h ) r u z d u g w u d q v i h u d g p l w w d q f h 6 \ p e r o , * 6 6 , ' 6 6 9 % 5 ' 6 6 9 w k 5 ' 6 2 1 _ < i v _ 7 h v w & r q g l w l r q 9 * 6 ? ? ? ? ?
7. 7. 7. 7. marking marking marking marking fig. fig. fig. fig. 7.1 7.1 7.1 7.1 marking marking marking marking www.freescale.net.cn www.freescale.net.cn 4/8 7 . 3 ' 0 d u n l q j 0 d u n l q j 0 d u n l q j 0 d u n l q j ) l j ) l j ) l j ) l j 0 d u n l q j 0 d u n l q j 0 d u n l q j 0 d u n l q j
8. 8. 8. 8. characteristics curves (note) characteristics curves (note) characteristics curves (note) characteristics curves (note) fig. fig. fig. fig. 8.1 8.1 8.1 8.1 i i i i d d d d - v - v - v - v ds ds ds ds fig. fig. fig. fig. 8.2 8.2 8.2 8.2 i i i i d d d d - v - v - v - v ds ds ds ds fig. fig. fig. fig. 8.3 8.3 8.3 8.3 i i i i d d d d - v - v - v - v gs gs gs gs fig. fig. fig. fig. 8.4 8.4 8.4 8.4 v v v v ds ds ds ds - v - v - v - v gs gs gs gs fig. fig. fig. fig. 8.5 8.5 8.5 8.5 |y |y |y |y fs fs fs fs | - i | - i | - i | - i d d d d fig. fig. fig. fig. 8.6 8.6 8.6 8.6 r r r r ds(on) ds(on) ds(on) ds(on) - i - i - i - i d d d d www.freescale.net.cn www.freescale.net.cn 5/8 7 . 3 ' & k d u d f w h u l v w l f v & x u y h v 1 r w h & k d u d f w h u l v w l f v & x u y h v 1 r w h & k d u d f w h u l v w l f v & x u y h v 1 r w h & k d u d f w h u l v w l f v & x u y h v 1 r w h ) l j ) l j ) l j ) l j , , , , ' ' ' ' 9 9 9 9 ' 6 ' 6 ' 6 ' 6 ) l j ) l j ) l j ) l j , , , , ' ' ' ' 9 9 9 9 ' 6 ' 6 ' 6 ' 6 ) l j ) l j ) l j ) l j , , , , ' ' ' ' 9 9 9 9 * 6 * 6 * 6 * 6 ) l j ) l j ) l j ) l j 9 9 9 9 ' 6 ' 6 ' 6 ' 6 9 9 9 9 * 6 * 6 * 6 * 6 ) l j ) l j ) l j ) l j _ < _ < _ < _ < i v i v i v i v _ , _ , _ , _ , ' ' ' ' ) l j ) l j ) l j ) l j 5 5 5 5 ' 6 2 1 ' 6 2 1 ' 6 2 1 ' 6 2 1 , , , , ' ' ' '
fig. fig. fig. fig. 8.7 8.7 8.7 8.7 r r r r ds(on) ds(on) ds(on) ds(on) - t - t - t - t a a a a fig. fig. fig. fig. 8.8 8.8 8.8 8.8 i i i i dr dr dr dr - v - v - v - v ds ds ds ds fig. fig. fig. fig. 8.9 8.9 8.9 8.9 c - v c - v c - v c - v ds ds ds ds fig. fig. fig. fig. 8.10 8.10 8.10 8.10 v v v v th th th th - t - t - t - t a a a a fig. fig. fig. fig. 8.11 8.11 8.11 8.11 p p p p d d d d - t - t - t - t c c c c (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) fig. fig. fig. fig. 8.12 8.12 8.12 8.12 dynamic input/output characteristics dynamic input/output characteristics dynamic input/output characteristics dynamic input/output characteristics www.freescale.net.cn www.freescale.net.cn 6/8 7 . 3 ' ) l j ) l j ) l j ) l j 5 5 5 5 ' 6 2 1 ' 6 2 1 ' 6 2 1 ' 6 2 1 7 7 7 7 d d d d ) l j ) l j ) l j ) l j , , , , ' 5 ' 5 ' 5 ' 5 9 9 9 9 ' 6 ' 6 ' 6 ' 6 ) l j ) l j ) l j ) l j & 9 & 9 & 9 & 9 ' 6 ' 6 ' 6 ' 6 ) l j ) l j ) l j ) l j 9 9 9 9 w k w k w k w k 7 7 7 7 d d d d ) l j ) l j ) l j ) l j 3 3 3 3 ' ' ' ' 7 7 7 7 f f f f * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p ) l j ) l j ) l j ) l j ' \ q d p l f , q s x w 2 x w s x w & k d u d f w h u l v w l f v ' \ q d p l f , q s x w 2 x w s x w & k d u d f w h u l v w l f v ' \ q d p l f , q s x w 2 x w s x w & k d u d f w h u l v w l f v ' \ q d p l f , q s x w 2 x w s x w & k d u d f w h u l v w l f v
fig. fig. fig. fig. 8.13 8.13 8.13 8.13 r r r r th th th th /r /r /r /r th(ch-c) th(ch-c) th(ch-c) th(ch-c) - t - t - t - t w w w w (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) fig. fig. fig. fig. 8.14 8.14 8.14 8.14 safe operating area safe operating area safe operating area safe operating area (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) fig. fig. fig. fig. 8.15 8.15 8.15 8.15 e e e e as as as as - t - t - t - t ch ch ch ch (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) fig. fig. fig. fig. 8.16 8.16 8.16 8.16 test circuit/waveform test circuit/waveform test circuit/waveform test circuit/waveform www.freescale.net.cn www.freescale.net.cn 7/8 7 . 3 ' ) l j ) l j ) l j ) l j u u u u w k w k w k w k 5 5 5 5 w k f k f w k f k f w k f k f w k f k f w w w w z z z z * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p ) l j ) l j ) l j ) l j 6 d i h 2 s h u d w l q j $ u h d 6 d i h 2 s h u d w l q j $ u h d 6 d i h 2 s h u d w l q j $ u h d 6 d i h 2 s h u d w l q j $ u h d * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p ) l j ) l j ) l j ) l j ( ( ( ( $ 6 $ 6 $ 6 $ 6 7 7 7 7 f k f k f k f k * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p * x d u d q w h h g 0 d [ l p x p ) l j ) l j ) l j ) l j 7 h v w & l u f x l w : d y h i r u p 7 h v w & l u f x l w : d y h i r u p 7 h v w & l u f x l w : d y h i r u p 7 h v w & l u f x l w : d y h i r u p 1 r w h 7 k h d e r y h f k d u d f w h u l v w l f v f x u y h v d u h s u h v h q w h g i r u u h i h u h q f h r q o \ d q g q r w j x d u d q w h h g e \ s u r g x f w l r q w h v w x q o h v v r w k h u z l v h q r w h g
package dimensions package dimensions package dimensions package dimensions unit: mm weight: 0.36 g (typ.) www.freescale.net.cn www.freescale.net.cn 8/8 7 . 3 ' 3 d f n d j h ' l p h q v l r q v 3 d f n d j h ' l p h q v l r q v 3 d f n d j h ' l p h q v l r q v 3 d f n d j h ' l p h q v l r q v 8 q l w p p : h l j k w j w \ s 3 d f n d j h 1 d p h v 7 2 6 + , % $ . 6 1 l f n q d p h ' 3 $ .
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